Mapping Function 1.0

Hi~~ How are your guys?

Today, I want to show you what is Mapping Function.

First,

 Mapping function can be determine as 3 topic below:

a)Direct Mapping

b) Associative Mapping

c) Set Associative Mapping

For examples,

Cache of 64K Bytes,

Cache block of 4 Bytes.

That's mean cache is organized as

(64/4)KB Lines of 4 bytes each.

Or,

16 MBytes main memory,

Main memory consists of

(16/4)MB Lines of 4 bytes each.

From the solutions at above,

∴Lines is equal to capacity of cache/main memory divide by the capacity of cache block.

Direct Mapping

-Each block of main memory maps to ONLY one cache line.
-Address is in 2 parts.
-Least Significant 'w' bits identify unique word/byte within a block of main memory.
-Most Significant 's' bits specify one of 2 power of 's' memory block.








Direct Mapping Address Structure

Direct Mapping Cache Organization

Well...Let me do a summary for the direct mapping..

According to the all diagram above,

We can know that:

a)Address length = (s+w) bits.

b)Block size=Line size= 2^(w) words or bytes.

c)Number of blocks in main memory = 2^(s)

d)Number of lines in cache = m = 2^(r)

e)Size of tag = (s-r) bits

Direct Mapping is simple and inexpensive but its fixed location for given block.


Youtube:Direct mapped function


To be continues....

                                                                                         Written by--®æŋ

Cache

Good Day to everyone =)

For this post is only discuss about the Cache. So that will not be so long post for your guys to reading =)

What is Cache?

Everyone only know the words of "Cache" or heard it before, but they might be do not know what is meant of the Cache and how it working inside the computer.

For today, i want to explain to your guys the "Cache",how it working and also the structure of cache and main memory :)

Cache is a small amount of fast memory. It is located and intermediate buffer between the CPU (Control Process Unit) and the normal Main Memory. Furthermore, cache is contain a copy of portions of main memory.

Cache Read Operation

↘Generate the RA(Reference Address) of word to be read.

↘Check if the word is inside the cache.

-If it is, deliver the word to processor.( Known as Cache Hit, it's fast)

-If not, block of main memory read into cache.( Known as Cache Miss, it's slow)

↘Locality of reference principle applies

-Future references likely to other words in block read into cache. 

Typically Cache Organization

Cache Structure & Main Memory Structure

In addition, 

that's no matter for the size of the cache.
But the more cache require, then that's more expensive.

Of course, the speed of cache is same as car engine.

More powerful car engine, the speed more faster.

More cache inside process, the speed also more faster. 

Last but not least, the larger cache has a larger gates involve-slow down

and take more time to check the data.

Well...  

I think your guys should gain some new information of cache 

after viewed my posted, right? xD

But remember that, "One is never too old to learn". 

For more information of cache, 

you may go to search it from the wiki-pedia or google by yourself. =)
Anyway,thanks for reading my posted. 

Have a nice day ! see ya~~

                                                                                                                                           Written by--®æŋ

Memory Hierarchy & Semiconductor Memory Types

Hello everyone !! ^_^

Today, i want to continues the tutorial with the Memory Hierarchy and the Semiconductor Memory Types.

When you want to go to purchase memory,(whatever RAM,internal/external hard disk,etc) 

I think your guys may consider about :

1) the capacity(how much for the amount you need?),

2) the cost(how much i need to pay for it?)

3) the speed/access time(how fast for the transfer speed,access speed?)

Is I am right?haha...

Memory Hierarchy Diagram----->

From up to down hierarchy:

•decreasing the cost per bit

•increasing the capacity

•increasing access time

•decreasing frequency of access of memory by proccessor

Sometimes, i am thinking...

Is that possible to build a computer which only use static RAM,

As that might be more faster and it would need no cache,although it would take a very large amount of cost.

Principle of Locality of Reference:

-During the course of the execution of a program, memory references by the processor tend to cluster

-Over a short period of time, processor is working with fixed clusters.

For example: loop,subroutines.As once a loop/subroutine is entered, there are repeated references to small set of instance.

We can consider to use two-level memory for example: 

--Level 2 memory contain all program instructions and data

--Place the current clusters in level 1

--From time to time, change the clusters to new –old clusters

swapping back to main memory

As the diagram below,

↓Semi-Conductor Memory↓

RAM( Random Access Memory)

-A form of computer data storage

-Read and Write only  in a predetermined order

-Volatile memory

-2 types: Static(SRAM) & Dynamic(DRAM)

DRAM(Dynamic RAM)

-Store each bit of data in a separate capacitor within an integrated circuit.

-Structural simplicity.

-Loses its data quickly when power is removed

-Cheaper

-Slower

-Need refresh circuits

-Main memory

DRAM Operation

# During the bit is read or written,the address line will be active.

-transistor switch closed

# Write

- High for 1, low for 0

- Signal apply to address line(change to capacitor)

# Read

-Select the address line, then transistor will turn on

-Charge from capacitor fed by bit line to sense amplifier

-Capacitor charge must be restored.

SRAM (Static RAM)

♂ Uses bis-table latching circuitry to store each bit.
♂ Periodically refreshed.
♂ More expensive.
♂ Less dense.
♂ Used in cache.
♂ Faster.
♂ Digital.
♂ Larger per bits.
♂ Complex construction.

SRAM Operation

~Standby
~Reading
~Writing

ROM(Read Only Memory)
∷It's permanent storage(non-volatile) and random access but can not be written to it.

∷Data stored in ROM cannot be modified (overwrite).

Types of ROM:


①PROM(Programmable ROM)
- Only program ONCE by user.
-Non-volatile.
-Programmed by burning the fuse using high current pulse.
-Flexible and convenient compared to ROM.

②EPROM(Erasable Programmable ROM)
∞ Re-programmable
∞ Erased by UV light
∞ More expensive than PROM
∞ Must be erased before to write it

③EEPROM
(Electrically Erasable PROM)
-No requirement of physically removed from the circuit for re-programming.
-Use special voltage level to erase data.
-Take much longer to write and read.
-More expensive than EPROM.
-Less dense.

④Flash Memory
- Special type of EEPROM
- Erase whole memory electrically, per block or per chip erasable.
- Suitable for used as solid state disk such as MemoryStick, SD(Scan Disk), MD(Micro Disk).







Ok. that's all for today. Hope your guys will learn something from my tutorial post. =)
I will continues to post the Cache at next tutorial post. See ya ! =D

                                                                 Written by--®æŋ

Introduction of Memory-System-Architecture and the Characteristics

Hi, everybody. =)

I am Raen and I am going to introduce the Memory-System-Architecture.

I will separate it into N topic there, so your guys might be read/view it as easy as well.

First, it must be the introduction part…(I very hate theory part which is very boring for me…T_T)

Ok, let’s begin the introduction. 

Memory-System-Architecture is used with the computer at 1960’s. 

It’s very expensive and unreliable for the elements involve vacuum tubes, switching elements, mercury delay. 

Not only that, magnetic core memories also expensive and slow. 

As we know that, memory capacity can be measured in bytes.

Next, there have 8 different characteristics of computer memory system as the below:

1) Location                         5) Performance

2) Capacity                         6) Physical type

3) Unit of transfer           7) Physical characteristics

4) Access method            8) Organisation

Location of memory (type of memory)

can be known as 3 parts: CPU, internal and external.

From the left diagram, registers is inside cpu and the internal memory location is involve main memory and cache.

Capacity is the understandable characteristic of memory. I think everyone already know what is meant of the capacity, right?
Ya, it’s meant the total amount of bits that can be stored in the memory.

For the internal memory, usually it will be expressed in number of bytes or Words and the external memory, typically it express to bytes only.

Unit of transfer has 3 different types:

1) Internal- determined by data bus width, may not equal to word.

2) External- Govern by block as it is larger than a word.

3) Addressable Unit- The fundamental data element size that can be addressed in the memory.

Access Methods:

1)  Sequential Access

→Data does not have a unique address
→Must read all data items in sequence until the desired item is found
→Access times are highly variable
→Example: Tape Drive Units

2) Direct Access

ΘData items have unique addresses
ΘAccess is done with using a combination of moving to a general memory "area" followed by a sequential access to reach the desired data item
ΘExample: Disk Drives

3) Random Access

# Each location has unique physical address
# Locations can be access in any order and all access times are the same
# "RAM" is more properly called read / write memory since this access technique apply to ROM as well
# Example: Main Memory

4) Associative Access

» A variation of random access memory

» Data items are accessed based on their contents rather than their actual location

» Search all data items in parallel for a match to a given search pattern

» All memory locations searched in parallel without regard to the size of the memory

» Extremely fast for large memory sizes

» Cost per bit is 5-10 times that of a “normal” RAM cell

» Example: cache.

Performance

3 performance parameters are used:

-Access time (latency)
≯Time between presenting the address and getting the valid 
≯Data and store or made available for use

-Memory cycle time
≯Cycle time is access time + recovery time

-Transfer rate

≯Rate at which data can be moved into or out of memory 
unit.

TN=TA + N/R 

≯where TN = Average time to read or write N bits≯

TA = Average access time

≯

N = Number of bits

≯

R = transfer rate, in bits per second (bps)

Physical Types & Characteristics

Typically, there is 3 physical types of memory:

 -Semiconductor memory

eg. RAM, ROM

 

-Magnetic

eg. Disk & Tape

-Optical

eg. CD & DVD

And 4 different physical characteristic:

-Volatile memory (R/W Memory)
information decays or lost when power is switched off

-Non volatile memory
no electrical power is needed (Magnetic surface memories/ROM)

-Non-Erasable 

-Power consumption

For the last characteristic is Organisation.

It's the physical arrangement of bits into words and there always not be used.

Finally... i have finish the part for the introduction.
hope your guys will understand my explanation.
See your guys in the next coming up post =)
thank you =D

Please kindly reply in comment there if you have any problem in this chapter.

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Pipelining

To understand how pipelining works

How Pipelining Works

Pipelined Laundry

Pipelining, a standard feature in RISC processors, is much like an assembly line. Because the processor works on different steps of the instruction at the same time, more instructions can be executed in a shorter period of time.

A useful method of demonstrating this is the laundry analogy. Let's say that there are four loads of dirty laundry that need to be washed, dried, and folded. We could put the the first load in the washer for 30 minutes, dry it for 40 minutes, and then take 20 minutes to fold the clothes. Then pick up the second load and wash, dry, and fold, and repeat for the third and fourth loads. Supposing we started at 6 PM and worked as efficiently as possible, we would still be doing laundry until midnight.

To study how pipelining can be used to build

fast processors

Pipelining and parallelism are 2 methods used to achieve concurrency.

—Pipelining increases concurrency by dividing a computation into a number of steps.

—Parallelism is the use of multiple resources to increase concurrency.

Pipelining is a key implementation technique used to build fast processors that can be seen in RISC architecture. It allows the execution of multiple instructions to overlap in time. 

In a non-pipelined processing, by contrast, the next data/instruction is processed after the entire processing of the previous data/instruction is complete.

There are TWO type of laundry in pipelined:

Sequential Laundry

However, a smarter approach to the problem would be to put the second load of dirty laundry into the washer after the first was already clean and whirling happily in the dryer. Then, while the first load was being folded, the second load would dry, and a third load could be added to the pipeline of laundry. Using this method, the laundry would be finished by 9:30.

   

If you glance back at the diagram of the laundry pipeline, you'll notice that although the washer finishes in half an hour, the dryer takes an extra ten minutes, and thus the wet clothes must wait ten minutes for the dryer to free up. Thus, the length of the pipeline is dependent on the length of the longest step. Because RISC instructions are simpler than those used in pre-RISC processors (now called CISC, or Complex Instruction Set Computer), they are more conducive to pipelining. While CISC instructions varied in length, RISC instructions are all the same length and can be fetched in a single operation. Ideally, each of the stages in a RISC processor pipeline should take 1 clock cycle so that the processor finishes an instruction each clock cycle and averages one cycle per instruction (CPI).

In a non-pipelined CPU, instructions are performed “one at a time”.ie. before an instruction is

begun, the preceding instruction is completed.

To implement instruction pipelining, desirable features of

(instruction set) IS:

—all instructions same length

—registers specified in same place in instruction

—memory operands only in loads or stores, i.e. RISC

But, it is not always the case in reality

To be aware of the limitations of pipelining

3 types of hazards:

-Resource hazards : HW cannot support this combination of instructions (single person to fold and put clothes away, washer-drier)

-Data hazards: Instruction depends on result of prior instruction still in the pipeline

-Data dependencies example

A = B + C

D = E + A

C = G x H

-Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps).

To understand characteristics and design of RISC

RISC: Reduced Instruction Set Computers

•Major advances in computer :

—The family concept

–Separates architecture from implementation

—Microprogrammed control unit

—Cache memory

—Solid State RAM

—Microprocessors

—Pipelining

–Introduces parallelism into fetch execute cycle

—Multiple processors

To contrast CISC and RISC

CISC and RISC

•Key features of CISC:

—Large number of predefined instructions making high level programming languages easy to design and implement.

—Supports microprogramming to simplify computer architecture

—

•Key features of RISC

—Limited and simple instruction set

—Large number of general purpose registers or use of compiler technology to optimize register use.

—Emphasis on optimizing the instruction pipeline