CMOS & External Memory

Hi everyone,

haiz...there is very sad and happy today.
Sad= This is the last post.
Happy= Finally I finished my mission already.

Anyway, hope all my post will help your guys something.


Let's start it together :)

What is CMOS?
CMOS actually is Complementary Metal Oxide Semiconductor.
-It requires very little power to retain its contents.
-It's able to store vital data of the computer system even when the power supply is turned off.
-It can hold the data involve floppy,hard-disk drives.
-It also able to kept the data of display system.(eg. date, time, system setup parameters.)




I believe that your guys have some idea with the external memory, right?

Normally, external memory can be separate with 3 common type:

1)Magnetic Disk

●Substrate used to be aluminium
●Improve surface uniformity
●Reduction in surface defects
●Lower flight heights
●Better stiffness and shock/damage resistance

Two types of the Magnetic Disk:

RAID(Redundant Array of Independent Disks)
-Lastest
-6 levels in common use but they don't imply hierarchical relationship.
-3 common characteristics:
  a)Set of physical disks viewed as single logical drive by O/S
  b)Data distributed across physical drives
  c)Can use redundant capacity to store parity information

-Removable (Floppy)

2)Optical Storage

-CD-ROM
-CD-Recordable(CD-R)
-CD-R\W
-DVD
-blu-ray

3)Magnetic Tape
●Serial access
●Slower
●Cheapest
●Backup and archive




Read and Write Mechanisms
⊕Record & retrieval though conductive coil which called a head
⊕During read/ write process, the head is stationary and the platter will rotates.

Characteristics

Head motion: Fixed (rare) or movable head
Disk portability: Removable or fixed (non-removable)
Magnetized-Coating Sides: Single or Double Sided
Platters: Single or Multiple platter
Head Mechanism
-Contact(Floppy)
-Fixed gap
-Aerodynamic

@The End@

Hope your guys will like my tutorial of Memory System Architecture.
If there got any problem or wrong, please kindly comment in my posted. I am very appreciated your suggestion.Thank you.


                                                                                                                                 Written by--®æŋ

Cache Replacement & Cache Write Policy

Hi guys~

Now i am going to introduce the cache replacement and its write policy.

Cache replacement is meant some existing cache memory will be delete to create space for the new entry when the cache is full already.

Here are the replacement algorithm:

1) Direct mapping
    -No choice
    -Replace line
    -Each block only maps to one line

2) Associative & Set Associative
    -Hardware implemented algorithm (speed)
    -Least recently Used(LRU)
    -First In First Out (FIFO)
    -Least Frequently Used (LFU)
    -Random

Write Policy
- Must not overwrite a cache block unless main memory is up to date.
- Multiple CPUs may have individual caches.
- I/O may address main memory directly.


There is 2 type of the write policy:

1)Write though

-Slows down write.
-Lots of traffic.
-All writes go to main memory as well as cache.

2)Write back

-Updates initially made in cache only.
-Updates bit for cache slot is set when update occurs.
-Other caches get out of sync.
-I/O must access main memory through cache.




Ya, that's all for the cache replacement & cache write policy.
Next post will be discuss about the CMOS & External Memory.
Thank you for viewing~~ :)


                                                                                            Written by--®æŋ

Solve the Mapping Function Question

Solve the Mapping Function Question:

Question 1

A computer system has a memory architecture made up of a main memory of 128 MB and

cache of 128 KB. In order to perform an efficient mapping function, the main memory is

arranged in block of 8 bytes. Draw the address structure for the different mapping functions as

below. (Indicate the fields and the number of bits required for each field.)

-Direct Mapping 

From the question, we know that:

Main memory = 128 MB = (128 x 1024 ) KB = (128 x 1024 x 1024 ) Bytes

Cache capacity = 128 KB = (128 x 1024 ) Bytes

Block capacity = 8 Bytes

Step 1:

Using "log A(Bytes) / log 2" to convert bytes to bits.

Main Memory = log (128 x 1024 x 1024 ) / log 2 = 27 bits

Lines in Cache = Cache capacity / Block Capacity =( 128 x 1024 ) / 8 =( 16 x 1024 ) bytes.

Convert it into bits. 

Lines in Cache =  (16 x 1024 ) bytes = log ( 16 x 1024 ) / log 2 =14 bits.

Block Capacity(Size) = 8 Bytes = log (8) / log (2) = 3 bits.

Step 2:

Find the Line, Tag and Word.

r = lines in cache, w = block size(capacity), s = main memory address length - block size.

r = 14 bits 

w = 3 bits

s = 27- 3 = 24 bits

Tag = s - r = 24 - 14 = 10 bits.

Step 3:

Finish the address structure.

Step 4:

Check the total ( tag + line + word) =main memory address length.

10(tag)+14(line)+3(word)=27(main memory address length).

If yes, mean that you do it correctly.

If no, maybe your calculation in the previous steps got problems.

-Associative Mapping

Main memory = 128 MB = (128 x 1024 ) KB = (128 x 1024 x 1024 ) Bytes

Cache capacity = 128 KB = (128 x 1024 ) Bytes

Block capacity = 8 Bytes

Step 1:

Using "log A(Bytes) / log 2" to convert bytes to bits.

Main Memory = log (128 x 1024 x 1024 ) / log 2 = 27 bits

Lines in Cache = Undetermined

Block Capacity(Size) = 8 Bytes = log (8) / log (2) = 3 bits.

Step 2:

Find the value of address structure.

s (tag) = main memory address length - block size , w = block size.

w = 3

s = 27 -3

s = 24

Step 3:

Finish the address structure.

Step 4:

Check the total ( tag + word) =main memory address length.

24(tag)+3(word)=27(main memory address length).

If yes, mean that you do it correctly.

If no, maybe your calculation in the previous steps got problems.

-'K' Way Set Associative Mapping

Main memory = 128 MB = (128 x 1024 ) KB = (128 x 1024 x 1024 ) Bytes

Cache capacity = 128 KB = (128 x 1024 ) Bytes

Block capacity = 8 Bytes

Let's say this is the 4 way set associative mapping.

So, k = 4.

Step 1:

Using "log A(Bytes) / log 2" to convert bytes to bits.

Main Memory = log (128 x 1024 x 1024 ) / log 2 = 27 bits

Lines in Cache = Cache capacity / Block Capacity =( 128 x 1024 ) / 8 =( 16 x 1024 ) bytes.

As there is 4 way set associative.

So, number of lines in set (k) is 4 .

Number of sets = d

Number of lines in cache(r) = k * d

So, we want to find the number of sets.

r = k * v,

d = r / k.

Number of sets = ( 16 x 1024 ) bytes / 4  = (4 x 1024 ) bytes

Convert it into bits. 

Number of sets =  (16 x 1024 ) bytes = log ( 4 x 1024 ) / log 2 =12 bits.

Block Capacity(Size) = 8 Bytes = log (8) / log (2) = 3 bits.

Step 2:

Find the value of address structure.

d = number of sets, w = block size(capacity), s = main memory address length - block size.

d = 12 bits 

w = 3 bits

s = 27- 3 = 24 bits

Tag = s - r = 24 - 12 = 12 bits.

Step 3:

Finish the address structure.

Step 4:

Check the total ( tag +set + word) =main memory address length.

12(tag)+12(set)+3(word)=27(main memory address length).

If yes, mean that you do it correctly.

If no, maybe your calculation in the previous steps got problems.

That's the way to solve the mapping function question.

Hope your guys will understand my steps as well.

Thank you. =)


                                                                                                                                  Written by--®æŋ

Mapping Function 3.0

Hi everyone, the Mapping Function 3.0 is arrived !! :D


MF 1.0 is for Direct Mapped function,
MF 2.0 is for Associative Mapped function.

So, MF 3.0 is for.....

Ya, MF 3.0 is for SET ASSOCIATIVE MAPPING FUNCTION !!!


As the name of this mapping function, the cache is divided into a number of sets.
And for each set, they contains a number of lines.
If that is 2 lines in one set, that's called 2 way set associative mapping.

Actually, we can mention that, the address structure of the direct mapped is almost same as the set associative mapping function.

The only difference is between the tag and word, for direct mapped is LINES ; for set associative mapping is SET.


Summary
のAddress Length = (s+w) bits
のBlock Size = Line Size = 2^(w) bytes/words
のNumber of blocks in memory = 2^(d)
のNumber of Lines in set = k ( k way set associative mapping)
のNumber of sets = v = 2^(d)
のNumber of lines in cache = k*v = k * 2^(d)
のSize of tag = (s-d) bits



Hooray~~
Finally, i finish all the mapping function.
For the new coming post, i will post how to solve the mapping question as well.
So, see your guys at next post~~

╭⌒╮¤　　　　　　`  
╭╭ ⌒╮ ●╭○╮　  
╰ ----╯/█∨█\ 　
 ~~~~~~~~∏~~~∏~~~~~~~~~~~


Youtube:K way set associative mapped function

                                                                                                               Written by--®æŋ

Mapping Function 2.0

Hello guys,

Let's us continues the mapping function 2.0  :)

Associative Mapping
-The replacement policy is free to choose any entry in the cache to hold the copy.
-Associative is a trade-off.
-There is examined to match every line's tag.
-Cache searching is expensive.

From the diagram, fully associative cache has more choice than direct mapped cache. As the direct mapped only can be link between cache and memory once.



















Associative Mapping Address Structure

Fully Associative Mapping Cache Organization

Summary:

Ⅰ-Address Length (Memory Length)= (s+w ) bits
Ⅱ-Block Size=Line Size=2^(w) bytes/Words
Ⅲ-Number of Lines in Cache = Undetermined
Ⅳ-Number of block in Memory = 2^(s)
Ⅴ-Size of Tag = 's' bits


Youtube:Fully Associative Mapped Function
To be continues again.... :)

                                                                                                                                             Written by--®æŋ

Introduction of I/O and Problem

The Computer I/O Architecture is its interface to the outside world and a means of controlling and managing I/O activities. The I/O system consists of I/O devices, device controllers (or I/O modules or I/O interviews) and driver software.

There a various input and output problems and they include;

•Wide variety of peripherals.
  Delivering different amounts of data
  Running at different speed
  Running in a different format
•All devices are slower than CPU and RAM
• They need I/O modules
  -Interface to CPU and Memory
  -Interface to one or more peripherals
• The encoding of the transmitted word must be that which is employed by the I/O device.

• Operating Rates
  -The CPU and Main Memory operate at many times the speed of I/O devices
• Timing and Control
 -Exchange of status signals between CPU and device.
 -Rate of transmission from device to CPU or vice-versa.
• Communication Link (Word Length)
– There are at least 25 different word lengths used in computers. The word lengths vary from 4 to 128 bits.The separation (or combination) of words (because of word length) into characters, bytes or other units presents a "word assembly" problem.CA - XVII - I/O - 5WORD-LENGTH DIFFER

Addressing Modes and Formats

These are the type of  Addressing Modes :

i) Immediate
ii) Direct
iii) Indirect
iv) Register
v) Register Indirect
iv) Displacement (Indexed)
iiv) Stack

Immediate Addressing 

This "addressing mode" does not have an effective address, and is not considered to be an addressing mode on some computers. This addressing is the simplest form of addressing which operand is part of instruction.

( Operand = address field )

Example: ADD 5

Add 5 to contents of accumulator

5 is operand

This mode can be used to define and use constants or set initial values of variables

Typically the number will be stored in twos complement form

The leftmost bit of the operand field is used as a sign bit

Advantage:

no memory reference other than the instruction fetch is required to obtain the operand, thus saving one memory or cache cycle in the instruction cycle

Disadvantage:

The size of the number is restricted to the size of the address field, which, in most instruction sets, is small compared with the word length

Direct Addressing

This requires space in an instruction for quite a large address. It is often available on Complex instruction set computing (CISC) machines which have variable-length instructions, such as x86.

Address field contains address of operand
Effective address (EA) = address field (A)

Example:  ADD A
Add contents of cell A to accumulator
Look in memory at address A for operand
Single memory reference to access data
No additional calculations to work out effective address
Limited address space

Indirect Addressing

Any of the addressing modes mentioned in this article could have an extra bit to indicate indirect addressing. Indirect addressing may be used for code or data. It can make implementation of pointers or references or handles much easier, and can also make it easier to call subroutines which are not otherwise addressable. Indirect addressing does carry a performance penalty due to the extra memory access involved.

Memory cell pointed to by address field contains the address of (pointer to) the operand

EA = (A)

Look in A, find address (A) and look there for operand

Example: ADD (A)

Add contents of cell pointed to by contents of A to accumulator

Advantage:

For a word length of N an address space of 2N is now available

Disadvantage:

Instruction execution requires two memory references to fetch the operand

One to get its address and a second to get its value

May be nested, multilevel, cascaded

Example: EA = (((A)))

Disadvantage is that three or more memory references could be required to fetch an operand

Hence slower

Register Addressing 

This "addressing mode" does not have an effective address and is not considered to be an addressing mode on some computers. Similar to direct addressing, the only difference is that the address field refers to a register rather than a main memory address.

Operand is held in register named in address filed

EA = R

Advantages:

Only a small address field is needed in the instruction

No time-consuming memory references are required

Disadvantage:

The address space is very limited

Register Indirect Addressing

The effective address for a Register indirect instruction is the address in the specified register.Similar to indirect addressing. The only difference is whether the address field refers to a memory location or a register

EA = (R)

Operand is in memory cell pointed to by contents of register R

Advantages and limitations:

-Basically same as indirect addressign

-Address space limitation of the address field is overcome by having that field refer to a word-length location containing an address

-Uses one less memory reference than indirect addressing

Relative Addressing

A version of displacement addressing. The effective address for a relative instruction address is the offset parameter added to the address of the next instruction. This offset is usually signed to allow reference to code both before and after the instruction.

R = Program counter, PC

EA = A + (PC)

i.e. get operand from A cells from current location pointed to by PC

c.f locality of reference & cache usage

Base-Register Addressing ( Displacement)

The base register could contain the start address of an array or vector, and the index could select the particular array element required. The processor may scale the index register to allow for the size of each array element. This could be used for accessing elements of an array passed as a parameter.

A- holds displacement

R- holds pointer to base address

R- may be explicit or implicit

Example: segment registers in 80x86

Indexed Addressing

This also requires space in an instruction for quite a large address. The address could be the start of an array or vector, and the index could select the particular array element required. The processor may scale the index register to allow for the size of each array element.

A = base

R = displacement

EA = A + R

Good for accessing arrays (iterative operations)

EA = A + R

R++ (increment R after each operation)

+------+-----+-----+--------------------------------+
   | load | reg |index|         address                | 
   +------+-----+-----+--------------------------------+
   
   (Effective address = address + contents of specified index register)

Stack Addressing

Operand is (implicitly) on top of stack
A stack is a reserved block of locations
e.g.
ADD
Pop top two items from stack and add

Instruction Formats

-Define the layout of the bits of an instruction, in terms of its constituent fields

-Must include an opcode and, implicitly or explicitly, indicate the addressing mode for each operand

-For most instruction sets more than one instruction format is used

For Instruction Length:

-Should be equal to the memory-transfer length or one should be a multiple of the other
-Should be a multiple of the character length, which is usually 8 bits, and of the length of fixed-point numbers

Instruction length can affected by : Memory size, Memory organization, Bus structure, CPU complexity, CPU ,speed .